`timescale 1ns/1ns
module uart_recive_test ;
reg   clk;
reg   rstn;
reg   uart_rxd;
wire  uart_done;
wire [7:0]  uart_data;
uart_recive u1(clk,rstn,uart_rxd,uart_done,uart_data);

initial
begin
  clk=1,rstn=0,
 